This invention relates to semiconductor devices having a mesa structure, and particularly to the configuration and fabrication of the mesa structure. The present invention is an improvement of those disclosed in my U.S. Pat. Nos. 4,740,477, 4,891,685 and 5,010,023, the subject matter of which is incorporated herein by reference.
These patents show rectifier devices comprising a mesa structure, particularly a frustum shaped mesa having a circular cross-section. The mesa contains various doped regions including an N.sup.+ N.sup.- junction which is generally parallel to the base plane of the mesa and which intercepts the side wall of the mesa. At the side wall, the surface of the N.sup.+ N.sup.- junction curves slightly upwardly. As explained in the patents, such curvature at the side walls reduces the electric field along the external surface of the mesa and, in general, provides more stable and reliable device operation.
The theory concerning surface voltage breakdown is presented by O. Melville Clark in U.S. Pat. No. 3,260,634 (Jul. 12, 1966) and by R. L. Davies, et al, in "Control of Electric Field at the Surface of P-N Junctions," IEEE Transactions on Electron Devices, July, 1964, pp. 313-323. These publications describe the use of mesas having sloped side walls. In the devices experimented with by Davies et al, sloped walls were obtained by mechanical means, e.g., grinding. However, in semiconductor devices using modern manufacturing techniques, the use of various mechanical means for providing mesa structures is quite impractical.
In my above cited patents, conventional photolithographic techniques are used involving anisotropic etching using a circular mask. The result, as shown in my patents, are frustro-conical mesas. A problem, however, is that using known anisotropic etching techniques, the actual slope of the mesa wall varies rather significantly from point to point around the periphery of the conical mesa. In general, the mesa conical wall has a slope of around 45 degrees, as measured from the mesa base plane, which is generally desirable, but the wall includes, as an inherent result of the anisotropic etching process, four bulges, disposed at 90 degrees from one another around the mesa periphery, where the wall slope increases to around 54 degrees. These variations in mesa wall slopes tend to provide non-uniform electrical fields around the periphery of the mesa, hence less stable operating conditions. In general, better devices, more easily mass produced, result if slope variations are not present or greatly reduced in size.
My patents also mention the use of a mesa having a generally square cross-section with rounded corners. Although not discussed at length in the patents, what was contemplated, as is typical in the semiconductor device art, is a mesa having four main side walls with each pair of adjacent side walls being interconnected by a curved corner wall. Typically, the side walls have a slope of about 54 degrees with respect to the base of the mesa (higher angular slopes correspond to steeper slope sides) and the corner walls have slopes of about 45 degrees. Again, such variations in mesa wall slopes are generally undesirable as tending to complicate manufacture of the devices.
In general, as discussed more fully hereinafter, more stable voltage breakdown characteristics are obtainable the smaller is the slope of the mesa because smaller slopes practically always result in smaller electric field values along the mesa side walls. However, when different slopes are present around the periphery of the mesa, the locations of surface intercepts of various junctions within the mesa also vary around the mesa periphery. Stable voltage breakdown characteristics require that the surface intercepts be passivated. It turns out, however, that proper passivation in most practical cases is a function of the location of the surface intercepts, and it is quite difficult and more expensive to design a single passivation scheme, suitable for use in mass production procedures, which is optimum for differently located surface intercepts.